A problem associated with leakage is shown in FIG. 1. FIG. 1 shows a typical CMOS inverter circuit 100. CMOS logic circuits are specified to be compatible not only for CMOS level (0 to 3.3 v) input signals but also TTL level (0.4 to 2.4 v) input signals. The TTL requirement typically causes leakage in PFET 101a. Specifically, if input node 103a has a TTL level logic high (V.sub.IH) input of 2.4 volts, the gate to source voltage of PFET 101a is 0.9 volts for a 3.3 volt supply node 105a. Such a voltage causes PFET 101a to turn "on".
However, since this is an inverting circuit, a logic high input ideally turns PFET 101a "off" and NFET 102a "on" resulting in ground voltage at output node 104a and no current flow from supply node 105a through PFET 101a.
If the TTL high input turns PFET 101a "on", leakage current flows from supply node 105a through PFET 101a (and most likely through NFET 102a to round). Obviously, an integrated circuit having potentially tens or hundreds of inverting or similar circuits will dramatically increase its power consumption if the leakage just described occurs. Thus, some form of addressing the leakage is necessary.
Some solutions for addressing this leakage problem boost the input voltage after its supplied at input node 103a such that the voltage at the gate of PFET 101a is high enough to cut off PFET 101a. However, this solution is not permissible with specifications requiring high input resistance. Thus the solution is not practicable in relation to most all industry requirements.
FIG. 2 shows a more robust design for addressing the leakage problem just described. Three stages are shown in circuit 200 of FIG. 2: a buffer stage 201a, a variable supply stage 202a, and a logical detect stage 204. As shown, the buffer stage supply node 210a is coupled to the variable supply stage output 211a at net 203; the buffer stage output 212a is coupled to the output node 104b and the logic detect stage input 213a at net 209; the logic detect stage output 214a is coupled to the variable supply stage input 215a at net 205 and the variable supply stage supply node 216a is coupled to supply node 105b. Input node 103b is coupled to buffer stage input 218a.
The buffer stage 201a is simply the inverter circuit 100 of FIG. 1. However, "buffer stages" may be almost any conceivable design having leakage. Variable supply stage 202a modulates the voltage or current applied to buffer stage supply node 210a in such a manner that voltage and/or current is limited when the logic detect stage 204 senses a logic low at output node 104b. A logic low at output node 104b means leakage is possible as input node 103b must be high. Thus the logic detect stage cuts off the power to buffer stage 201a if leakage is possible. Buffer stage supply node 210a reverts back to the supply voltage (i.e. voltage at supply node 105b) when the logic detect stage 204 senses a logic high. That is, the supply voltage returns when leakage is impossible (input node 103b is low).
Thus, the logical detect stage 204 merely detects the logic level at buffer stage output 212a.
In the example of circuit 200, variable supply stage 202a has a switch transistor 207 and a decoupling capacitor 208. Ideally, when there is no possibility of leakage (i.e., when input node 103b is low), switch transistor 207 is on and the full supply voltage appears at the buffer stage supply node 210a. When leakage is possible (i.e., when input node 103b is high), switch transistor 207 is off leaving the decoupling capacitor 208 as the sole voltage source at the source of PFET 101b. The decoupling capacitor 208 voltage is then a function of the amount of leakage through PFET 101b, if any exists.
Problems exist, however, if one employs a logic detect stage 204. One problem is that the voltage at buffer stage supply node 210a is cut off from supply node 105b even if no actual leakage exists. The voltage is cut off if leakage is merely possible. That is, if a CMOS level high signal (approx. 3.3) is placed at input node 103b the switch transistor 207 is cut off even though there is no risk of leakage through transistor 101b. Anytime the voltage at buffer stage supply node 210a is dropped, a corresponding reduction in circuit speed is realized. That is, at output node 104b there is typically some capacitive loading 217. Anytime the voltage at buffer stage 201a supply node 210a is reduced, the charge/discharge time at output node 104b lengthens. Thus use of a logic detect stage 204 results in slower circuit speed not only for TTL level but also CMOS level input signals at input node 103b.
A further problem involves decoupling capacitor 208 as shown and described with reference to FIG. 3. FIGS. 3a-3c show critical voltages for cases where the high to low transition of the input voltage at input node 103b is ideal. FIGS. 3d-3f show the same critical voltages if the input voltage transition is less than ideal. Use of circuit 200 of FIG. 2 results in improper circuit operation for the input voltage shown in FIG. 3d. Essentially circuit 200 only works for synchronous applications and not asynchronous applications.
"Synchronous" simply means some kind of clocking or other mechanism exists whereby critical voltages must make logic transitions (either high to low or low to high) within some limited time period. "Asynchronous" environments have no such limited time period. Therefore, it is possible for practically unlimited transition time periods (such as that shown in FIG. 3d) within asynchronous environments but not in synchronous environments (i.e., the transition shown in FIG. 3a is almost necessary in synchronous environments).
FIG. 3a is a schematic depiction of an ideal TTL input voltage signal. The fall time from the voltage high level (V.sub.IH =2.4 volts) to the logic low level (V.sub.IL =0.4 volts) is zero. Better put, the transition from logic high to logic low is instantaneous. For instantaneous transitions the source voltage of PFET transistor 101b and the output node 104b voltage are shown in FIGS. 3b and 3c respectively.
As shown in FIG. 3b, while the input node 103b voltage is at a TTL level logic high (V.sub.IH =2.4 v), the source voltage of PFET 101b slightly less than V.sub.IH +V.sub.T (=2.4+0.7=3.1). This voltage results from the fact that, as discussed, switch transistor 207 is cut off by logic detect stage 204 when logic level high signals are placed input node 103b. At the time switch transistor 207 is cut off, which is shortly after the input voltage transitions from low to high (not shown in FIG. 3a or 3d), the voltage at decoupling capacitor 208 (and the source of PFET 101b) is the full supply voltage at node 105b. This causes PFET 101b to leak. The source of leakage current is decoupling capacitor 208 since transistor 207 is cut off. As PFET 101b continues to leak, charge is continually drawn from decoupling capacitor 208 resulting in a continual voltage drop in decoupling capacitor 208 voltage and continued drop at the source of PFET 101b. This gradual decay in decoupling capacitor 208 voltage stops at the point where PFET 101b becomes cut off (i.e., when slightly less than the threshold voltage (V.sub.T) appears across the gate-to-source region of PFET 101b.) The source of PFET 101b is then "stuck" at slightly less than V.sub.IH +V.sub.T as no current path to ground exists from decoupling capacitor 208. This is the state shown in FIG. 3b prior to the high to low transition at t.sub.oa.
Once there is a transition at input node 103b from logic high to logic low, as shown at t.sub.oa in FIGS. 3a-c, NFET 102b converts from on to off and PFET 101b turns from off to on as there is an instantaneous gate-to-source voltage of slightly less than 3.1 volts across transistor 101b at time t.sub.oa. With transistor 101b "on" at time t.sub.oa the decoupling capacitor 208 voltage (3.1 volts) appears at output node 104b as shown in FIG. 3c. This enables inverter 206 of logic detect stage 204 to flip and place a logic level low signal at the variable supply stage input 215a at time t.sub.oa +.DELTA.t where .DELTA.t is the propagation delay in logic detect stage 204. At time t.sub.oa +.DELTA.t switch transistor 207 is turned "on" which ultimately charges up decoupling capacitor 208 to the supply voltage of supply node 105b. Thus FIGS. 3a-3c show proper operation when the transition at input node 103b is ideal.
FIGS. 3d-3f show circuit operation when the input voltage (V.sub.IN) transition is less than ideal. Specifically, when there is a long fall time from logic high to logic low (t.sub.1a -t.sub.oa). In this case the voltage at decoupling capacitor 208 is slightly less than 3.1 volts when the input voltage at input node 103b is high. In a somewhat iterative process, the decoupling capacitor 208 voltage (i.e., source voltage of PFET 101b) gradually decays along with the input voltage as shown in FIG. 3e.
The iterative process occurs as follows: first the decoupling capacitor decays to a voltage slightly less than V.sub.IH +V.sub.T by time t.sub.oa as already discussed. Then, the input node 103b voltage (V.sub.IN) drops slightly to V.sub.IH -.DELTA.V in accordance with the gradual decay shown in FIG. 3d. Once the input voltage drops to V.sub.IH -.DELTA.V, the gate to source voltage of PFET 101b changes from slightly less than V.sub.T to slightly more than V.sub.T. Thus transistor 101b changes from off to on and begins to leak charge out of decoupling capacitor 208. The leakage continues until the decoupling capacitor 208 voltage drops to slightly less than V.sub.IH +V.sub.T -.DELTA.V which turns transistor 101b off. Thus by this process, the decoupling capacitor 208 voltage drops .DELTA.V identically with the input voltage. As V.sub.IN continuously drops, so does the voltage at the source of transistor 101b.
Ultimately, the ramp down of the input voltage at input node 103b falls below V.sub.T (approximately equal to 0.7 v). At this point NFET 102b turns off and, ideally, PFET 101b turns on. However, because the source voltage of transistor 101b (i.e., the voltage across the decoupling capacitor 208) has been dragged down by the decaying input voltage there is simply no charge left in decoupling capacitor 208 to raise the output node 104b to a logic high level. Thus, inverter 206 never sees a high input and never switches transistor 207 on. Because input voltages such as those shown in FIG. 3d are conceivable within asynchronous environments solutions for the leakage problem such as those shown in FIG. 2 are simply unacceptable for asynchronous applications. Thus what is needed is an approach that operates within an asynchronous environment and/or does not limit circuit speed for CMOS level input signals.